An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

This article presents an open-source framework for emulating mixed-signal chip designs on a field-programmable gate array (FPGA). It includes Python-based synthesizable model generator blocks (msdsl), fixed-point and floating-point SystemVerilog library representing real numbers (svreal), tool that generates emulator control infrastructure automates the FPGA build process (anasymod). The features efficiently modeling analog dynamics, nonlinearity, noise, often making use of compile-time caching to reduce required computational resources FPGA. We demonstrate framework’s generality by discussing three applications: 1) high-speed link receiver (DragonPHY); 2) firmware-controlled flyback converter; 3) NFC-powered chip. Our makes it easy emulate these systems, while providing runtimes 2–3 orders magnitude faster than CPU simulations with real-number functional models.